NXP Semiconductors /LPC43xx /SGPIO /OUT_MUX_CFG[1]

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Interpret as OUT_MUX_CFG[1]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DOUT_DOUTM1)P_OUT_CFG 0 (GPIO_OE_STATE_SET_B)P_OE_CFG 0RESERVED

P_OUT_CFG=DOUT_DOUTM1, P_OE_CFG=GPIO_OE_STATE_SET_B

Description

Pin multiplexer configuration registers.

Fields

P_OUT_CFG

Output control of output SGPIOn. All other values are reserved.

0 (DOUT_DOUTM1): dout_doutm1 (1-bit mode)

1 (DOUT_DOUTM2A): dout_doutm2a (2-bit mode 2a)

2 (DOUT_DOUTM2B): dout_doutm2b (2-bit mode 2b)

3 (DOUT_DOUTM2C): dout_doutm2c (2-bit mode 2c)

4 (GPIO_OUT_LEVEL_SET): gpio_out (level set by GPIO_OUTREG)

5 (DOUT_DOUTM4A): dout_doutm4a (4-bit mode 4a)

6 (DOUT_DOUTM4B): dout_doutm4b (4-bit mode 4b)

7 (DOUT_DOUTM4C): dout_doutm4c (4-bit mode 4c)

8 (CLK_OUT): clk_out

9 (DOUT_DOUTM8A): dout_doutm8a (8-bit mode 8a)

10 (DOUT_DOUTM8B): dout_doutm8b (8-bit mode 8b)

11 (DOUT_DOUTM8C): dout_doutm8c (8-bit mode 8c)

P_OE_CFG

Output enable source. All other values are reserved.

0 (GPIO_OE_STATE_SET_B): gpio_oe (state set by GPIO_OEREG)

4 (DOUT_OEM1_1_BIT_MOD): dout_oem1 (1-bit mode)

5 (DOUT_OEM2_2_BIT_MOD): dout_oem2 (2-bit mode)

6 (DOUT_OEM4_4_BIT_MOD): dout_oem4 (4-bit mode)

7 (DOUT_OEM8_8_BIT_MOD): dout_oem8 (8-bit mode)

RESERVED

Reserved.

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